`timescale 10ns/1ns
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:15:57 06/04/2012 
// Design Name: 
// Module Name:    core 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Controler(
		input CLK, nRST,
		input execute,
		input [7:0] cmd,

		output reg LS_Reset,
		output reg LS_RD_Status
    );

reg dly_execute, next_dly_execute;
reg next_LS_Reset;
reg next_LS_RD_Status;

always @(posedge CLK or negedge nRST) begin
	if(!nRST) begin
		dly_execute <= 0;
		LS_Reset <= 0;
		LS_RD_Status <= 0;
	end else begin
		dly_execute <= next_dly_execute;
		LS_Reset <= next_LS_Reset;
		LS_RD_Status <= next_LS_RD_Status;
	end
end

always @* begin
	next_dly_execute = execute;
	next_LS_Reset = 0;
	next_LS_RD_Status = 0;

	if(!execute & dly_execute) begin
		case(cmd)
			/*Short command*/
			//0x00: Reset FPGA
			8'h00 : next_LS_Reset = 1;

			//8'h3F - reserve
			8'h80 : next_LS_RD_Status = 1;
		endcase
	end
end

endmodule
